我购买的Geil 白金条 2Gx2 用SPD Tool 0.62察看信息如下
Number of Serial PD Bytes written during module production 128
Total number of Bytes in Serial PD device 256
Fundamental Memory Type DDR2 SDRAM
Number of Row Addresses on this assembly 14
Number of Column Addresses on this assembly 10
Number of DIMM Ranks 2
Card On Card Yes
DRAM Package Planar
Module Height 30.0 mm
Module Data Width 64
Voltage Interface Level of this assembly SSTL 1.8V
SDRAM Cycle time at Maximum Supported CAS Latency 2.50 ns (400 MHz)
SDRAM Access from Clock 0.40 ns
DIMM error detection/correction features None
Refresh Rate Reduced 7.8 uS
Primary SDRAM Width 8
Error Checking SDRAM Width 0
Burst Lengths Supported 4, 8
Number of Banks on SDRAM Device 8
CAS Latencies Supported 4, 5
Module Thickness <4.10 mm
DIMM Type UDIMM
Analysis Probe Installed No
FET Switch Available No
Number of PLLs on the DIMM 0
Numer of Active Registers on the DIMM 0
Support Weak Driver Yes
Supports 50 Ohm ODT Yes
Supports PASR (Partial Array Self Refresh) Yes
Minimum Clock Cycle at CLX-1 3.75 ns (267 MHz)
Maximum Data Access Time (tAC) from Clock at CLX-1 0.50 ns
Minimum Clock Cycle at CLX-2 Undefined
Maximum Data Access Time (tAC) from Clock at CLX-2 Undefined
Minimum Row Precharge Time (tRP) 12.50 ns
Minimum Row Active to Row Active delay (tRRD) 7.50 ns
Minimum RAS to CAS delay (tRCD) 12.50 ns
Minimum Active to Precharge Time (tRAS) 45 ns
Module Rank Density 1 GB
Address and Command Input Setup Time Before Clock (tIS) 0.17 ns
Address and Command Input Hold Time After Clock (tIH) 0.25 ns
Data Input Setup Time Before Strobe (tDS) Undefined
Data Input Hold Time After Strobe (tDH) 0.12 ns
Write recovery time (tWR) 15.00 ns
Internal write to read command delay (tWTR) 7.50 ns
Internal read to precharge command delay (tRTP) 7.50 ns
Minimum Active to Active/Refresh Time (tRC) 57.50 ns
Minimum Refresh to Active/Refresh Command Period (tRFC) 127.50 ns
Maximum device cycle time (tCKmax) 8.00 ns
Maximum skew between DQS and DQ signals (tDQSQ) 0.20 ns
Maximum Read Data Hold Skew Factor (tQHS) 0.30 ns
PLL Relock Time Undefined
SPD Revision 1.2
Manufacturer’s JEDEC ID Code Golden Empire
Module Manufacturing Location 84
Module Part Number CL5-5-5 DDR2800
Module Revision Code 4100
Module Manufacturing Date Week 03 08
Module Serial Number 00000000
[ 本帖最后由 Meditation 于 2008-2-6 10:49 编辑 ]
