cio

6000+钱买6320更强

zwj051484

引用:

原帖由 aikesi 于 2007-8-23 19:43 发表
内存现在能到多少稳定，电压是多少？

我的白金条只能马马虎虎 1.9V到DDR1000   

报上SPD的信息来。

最好有个Thaiphoon.Burner的SPD读取报告。嘿嘿！！

cio

不好意思，又拿肉出来，晒了

aikesi

那个什么信息怎么看？

aikesi

我只会这么截图

cio

EasyTune5

aikesi

没装

那东西我基本上不装的

喜欢干净的系统。。

测试一下，成绩还不错

hypercube

intel板贵！

aikesi

东西到哪里了？？？



今天一天在家，没去关心过

aikesi

这个主板 880元

稍微还是有点贵

cio

cio

引用:

原帖由 aikesi 于 2007-8-23 20:14 发表
这个主板 880元

稍微还是有点贵  

+100买MSI的板子

cio

引用:

原帖由 aikesi 于 2007-8-23 20:14 发表
东西到哪里了？？？



今天一天在家，没去关心过

http://www.sto.cn/querybill/webform1.aspx?wen=268337716933%0D%0A268337716931&Submit2=%B2%E9%D1%AF

hypercube

当时买的时候amd 570sli是amd系列中比较好的了，才650元，本来想买590sli的amd最高端，也只有13xx元而已，因为买了g80就没买，相对而言，要是我不买570sli，买intel的，就会去看p35什么的，还要一线的，价格就要贵不少了，更不要谈高端主板了。而且我觉得intel产品更新的要比amd快.

aikesi

MANUFACTURING DESCRIPTION

Manufacturer's JEDEC ID Code: Golden Empire (GEIL)
Module Manufacturing Location: 54h
Module Part Number: CL5-5-5DDR2-800  
Module Revision Code: 4100h
Module Manufacturing Date: Week 5, 2007
Module Serial Number: 00000000h
LEGITIMATE ARCHITECTURES

Fundamental Memory Type: DDR2 SDRAM
DIMM configuration type: Non-ECC/Parity
DIMM type information: UDIMM (133.35 mm)
Number of Row Addresses: 14
Number of Column Addresses: 10
Number of Ranks: 2
Module Rank Density: 512 MB
Number of Banks on SDRAM Device: 4
Module Data Width: 64 bits
Primary SDRAM Width: x8
Error Checking SDRAM Width: N/A
Voltage Interface Level: SSTL 1.8 V
Refresh Rate/Type: 7.8 us Self Refresh
DDR SDRAM DIMM Height: 30.0 mm
TIMING SPECIFICATIONS

Burst Lengths Supported: 4, 8
CAS# Latencies Supported (tCL): 3T, 4T, 5T
Cycle time at Max CAS Latency: 2.5 ns
SDRAM Access from Clock (tAC): 0.40 ns
Minimum Clock Cycle at tCL = X - 1: 3.13 ns
Max Data Access Time at tCL = X - 1 (tAC): 0.50 ns
Minimum Clock Cycle at tCL = X - 2: 5.0 ns
Max Data Access Time at CL = X - 2 (tAC): 0.60 ns
Minimum Active to Precharge Time (tRAS): 37.0 ns
Minimum RAS to CAS delay (tRCD): 15.0 ns
Minimum Row Precharge Time (tRP): 15.0 ns
Min Active to Active/Auto Refresh Time (tRC): 57.0 ns
Min Auto Ref to Active/Auto Refresh (tRFC): 105.0 ns
Min Row Active to Row Active delay (tRRD): 7.50 ns
Write Recovery Time (tWR): 15.0 ns
Internal write to read command delay (tWTR): 7.50 ns
Internal read to precharge command delay (tRTP): 7.50 ns
Addr and CMD Input Setup Time Before Clock (tIS): 0.15 ns
Addr and CMD Input Hold Time After Clock (tIH): 0.22 ns
Data Input Setup Time Before Clock (tDS): 0.05 ns
Data Input Hold Time After Clock (tDH): 0.17 ns
Device Max device cycle time (tCKmax): 8.0 ns
Max skew between DQS and DQ signals (tDQSQ): 0.20 ns
Max Read Data Hold Skew Factor (tHQS): 0.24 ns
SPD PROTOCOL

Number of bytes written into SPD: 128
Total number of bytes of SPD: 256
SPD Revision: 1.2
Checksum for Bytes 0-62: 34h
SUMMARY SPECIFICATION

Module Type: DDR2 SDRAM PC2-6400 (DDR2-800)
Module Size: 1024 MB
Frequency tCL tRCD tRP tRAS tRC tRFC tRRD tWR tWTR tRTP
400 MHz 5.0 6 6 15 23 42 3 6 3 3
267 MHz 4.0 4 4 10 16 28 2 4 2 2
200 MHz 3.0 3 3 8 12 21 2 3 2 2

aikesi

这个软件看来蛮好玩的

那天试试看

aikesi

引用:

原帖由 cio 于 2007-8-23 20:17 发表

http://www.sto.cn/querybill/webf ... ubmit2=%B2%E9%D1%AF

真是曲折的道路

杭州。。。。

zwj051484

aikesi

Cio看来得罪MM了

cio

是GG

zwj051484

和我的不太一样呢。昏迷
MANUFACTURING DESCRIPTION

Manufacturer抯 JEDEC ID Code: Golden Empire (GEIL)
Module Manufacturing Location: 54h
Module Part Number: CL5-5-5DDR2-800  
Module Revision Code: 4100h
Module Manufacturing Date: Week 50, 2007
Module Serial Number: 00000000h
LEGITIMATE ARCHITECTURES

Fundamental Memory Type: DDR-II SDRAM
DIMM configuration type: Non-ECC/Parity
DIMM type information: UDIMM (133.35 mm)
Number of Row Addresses: 14
Number of Column Addresses: 10
Number of DIMM Banks: 97
Module Bank Density: 512 MB
Number of Banks on SDRAM Device: 4
Module Data Width: 64 bits
Primary SDRAM Width: x8
Error Checking SDRAM Width: N/A
Voltage Interface Level: SSTL 1.8V
Refresh Rate/Type: 7.8 us Self Refresh
DDR SDRAM DIMM Height:  
TIMING SPECIFICATIONS

Burst Lengths Supported: 4, 8
CAS# Latencies Supported (tCL): 3.5T, 3T, 2.5T
Cycle time at Max CAS Latency: 2.5 ns
SDRAM Access from Clock (tAC): 0.40 ns
Minimum Clock Cycle at tCL = X - 0.5: 3.13 ns
Max Data Access Time at tCL = X - 0.5 (tAC): 0.50 ns
Minimum Clock Cycle at tCL = X - 1: 5.0 ns
Max Data Access Time at CL = X - 1 (tAC): 0.60 ns
Minimum Active to Precharge Time (tRAS): 37.0 ns
Minimum RAS to CAS delay (tRCD): 15.0 ns
Minimum Row Precharge Time (tRP): 15.0 ns
Min Active to Active/Auto Refresh Time (tRC): 57.0 ns
Min Auto Ref to Active/Auto Refresh (tRFC): 105.0 ns
Min Row Active to Row Active delay (tRRD): 7.50 ns
Write Recovery Time (tWR): 15.0 ns
Internal write to read command delay (tWTR): 7.50 ns
Internal read to precharge command delay (tRTP): 7.50 ns
Addr and CMD Input Setup Time Before Clock: 0.15 ns
Addr and CMD Input Hold Time After Clock: 0.22 ns
Data Input Setup Time Before Clock: 0.05 ns
Data Input Hold Time After Clock: 0.17 ns
Device Max device cycle time (tCKmax): 32.0 ns
Max skew between DQS and DQ signals: 0.20 ns
Max Read Data Hold Skew Factor: 0.24 ns
Back-to-Back Random Col Access (tCCD): 0T
SPD PROTOCOL

Number of bytes written into SPD: 128
Total number of bytes of SPD: 256
SPD Revision: 0.0
Checksum for Bytes 0-62: 34h
SUMMARY SPECIFICATION

Module Type: DDR-II SDRAM
Module Size: 49664 MB
Frequency tCL tRCD tRP tRAS tRC tRFC tRRD tWR tWTR tRTP
400 MHz 3.5 6 6 15 23 42 3 7 3 3
233 MHz 3.0 4 4 9 14 25 2 4 2 2
200 MHz 2.5 3 3 8 12 21 2 4 2 2

zwj051484

引用:

原帖由 cio 于 2007-8-23 20:47 发表
是GG

呵呵。他男女不分滴，不管他。挖卡卡

zwj051484

你的白金是不是老白金啊？不是CL=4/5的吧？

aikesi

报告

看不到

机器点着，没法看